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![[Flowgic - Chip]](images/chip.gif)
AXI Bus Extender IP Core
AMBA AXI from ARM Holdings is an high performance on-chip bus architecture. Wide datapath versions of
of the AXI are not amenable to extensions beyond a single chip/FPGA. Flowgic's AXI Bus Extender(ABE) core makes it
possible to extend AXI bus
across two chips with very few package pins. ABE core is built using Flowgic's Interlaken Controller(IL)
core, which is a flexible, high-bandwidth, packet transport mechanism for chip-to-chip communication
![[Flowgic - ae_block]](images/ae_block.gif)
View Larger PictureKey Features
- Supports 64-bit and 128-bit AXIdata channels
- Transparently bridges transactions, maintaining AXI ordering requirements
- Makes use of Interlaken controller, a flexible and robust, chip-to-chip packet communication protocol controller
- Maps AXI channels to independent Interlaken channels
- Provides an additional high-priority external message channel to user logic for communicating control and status information
- Dedicated high-priority internal message channel for Heartbeat and health status reporting
- Built-in arbiter that accords highest priority to message channels and round-robin arbitration for AXI channels
- Simple, synchronous interface to user logic
- High-speed SERDES lanes or lower-speed LVDS lanes for chip-to-chip interface
- Extensive error reporting and diagnostics
Advantages
- Low Pin Count
- Low Latency
- Low Gate Count
- Flexible Design
- Designed for Reuse & Testability
- Proven Design Methodology
- Customization Options
Deliverables
- Functional Specification
- RTL Database
- Functional Verification Environment
- Synthesis Scripts
- Timing Report
- User Guide
Contact
For licensing/more information, contact sales or call +1 (510)656-4524.