...harnessing the power of logic.

Interlaken Controller IP Core

Flowgic's Interlaken IP core is an efficient implementation of Interlaken Protocol version 1.2. Interlaken IP core is designed for flexibility, robustness, scalability and is available in 64(10-20 Gb/s), 128(20-40Gb/s), 256(40-80Gb/s) and 384(80-120Gb/s) bit datapath variants.

[Flowgic - il_block] View Larger Picture

Key Features

  • Flexible number of lanes and each lane operating at data rates up to 10.3125 Gbs
  • Support for up to 256 channels
  • Implements out-of-band and in-band flow control
  • Optional full-packet mode support
  • Insertion of BCW/ICW and packet delineation using BCW/ICW
  • Additional ICW insertion to meet BurstShort
  • Implements rate-matching logic with token bucket
  • Efficient scheduling of packets from different channels
  • 64b/67b encoding/decoding
  • Set/reset scrambler
  • Metaframing/deframing
  • Simple system-side interface
  • Optional gear box to work with SerDes with 32 bit interfaces
  • Lane-to-lane deskew logic that can handle up to 107/214 UI skew
  • Extensive statistics
  • Comprehensive error reporting/handling
  • Per-lane test patterns
  • Support unidirectional implementations: out-of-band status channel which will carry both FC and DI information

Advantages

  • Low Gate Count
  • Flexible Design
  • Designed for Reuse & Testability
  • Proven Design Methodology
  • Customization Options

Deliverables

  • Functional Specification
  • RTL Database
  • Functional Verification Environment
  • Synthesis Scripts
  • Timing Report
  • User Guide

Contact

For licensing/more information, contact sales or call +1 (510)656-4524.

Spotlight

- A unique AMBA AXI solution from Flowgic extends the bus between chips.

- Flowgic offers 10 Gb/s Ethernet MAC and 10-120 Gb/s Interlaken Controller IP cores.

- Download for free Synthesizeable IP cores -- 10 Gb/s Interlaken and Ethernet MAC.

- Access to full-featured RegEx, a comprehensive Control/Status Register generation Tool, is now Free.